It is common in the industry to fabricate a plurality interconnected integrated circuits on a single semiconductor chip. In many applications, the chip is attached to a packaging substrate by a method and structure known as flip chip bonding where interconnecting circuitry on the face of the chip is reflow soldered directly to the substrate. (For a description of "Flip Chip Bonding", see, for example, U.S. Pat. Nos. 3,429,040 and 3,517,278.) Typically, chip sizes may vary from 0.040 inch square to 0.125 inch square and larger. Increasing sophistication in the semiconductor industry has resulted in the increase in size of individual chips as well as an increase in the number and circuit density of chips mounted on a single substrate or packaging structure. In order to connect circuitry on the chips to external circuits a plurality of contact points on the chip must be accurately aligned to matching contact points on the substrate. The number of contact points, or C4 connections, required depends upon the circuit density and complexity of integrated circuit chips. The number of solder connections between a integrated circuit chip flip chip bonded to the substrate of a packaging structure may be one hundred to two hundred or greater.
A significant problem in the manufacture of integrated circuit modules is the high cost of individual chips and/or modules, where a module may be defined as an integrated circuit packaging structure. It is no longer economically feasibly to disgard modules which contain defective chips, bonds and/or connector pins due to the high dollar value involved. Therefore, it has become very necessary to devise methods of repairing modules by replacing defective chips, bonds and/or connector pins without affecting quality of adjacent chips and/or connector pins. Other problems including misalignment of chips and defective bonding also require the use of repair techniques. While batch furnace methods and techniques are satisfactory to originally bond all chips and connector pins, these methods are not acceptable as repair techniques. Individual chips must be removable without effecting the integrity of adjacent chip bonding or the quality of chip circuitry. An effective repair technique must include a means for applying a concentrated source of heat to an individual chip at such a rate as to not overheat an adjacent chip by conduction through the substrate. Various methods of applying a concentrated source of heat to an individual chip have been previously suggested. Typical heat sources include laser, electron beam, infrared, resistance heating, hot gas and flame. All these sources are capable of supplying a sufficient quantity of heat but in practice it has been found that accurate control of the temperature of the chips is extremely difficult due to the varying nature of the diffusion bond between the chips, solder alloy and substrate. Additionally, many sources, for example hot gas, are difficult to apply to a limited area without adversely affecting adjacent chips. In other methods, the heat applied to defective chips is so intense that removed chips are completely destroyed and therefore unavailable for reuse or quality control evaluation purposes.
Another problem in the repair of modules presented by the nature of diffusion bonding alloys is that only a limited number of solder reflow cycles are permissible without destroying the integrity of the metallurgical bond due to diffusion between the solder alloy and the chip or substrate base metallurgy. In order to achieve the maximum number of repair cycles for a single multi-chip substrate, heating techniques such as reflowing all the chips on the substrate in a manner similar to that used to originally bond the chips is unsatisfactory due to the limitation on the number of reflow cycles each chip is capable of safely withstanding. U.S. Pat. No. 3,735,911 is directed to an integrated circuit chip repair tool for bonding or removing reflow soldered chips on a multi-chip substrate.
The present trends in microelectronics towards large scale integration require the use of semiconductor packages that interconnect and support a plurality of semiconductor devices. Such a package may include, for example, a multi-layer ceramic substrate with many semiconductor devices solder bonded to interconnection metallurgy in the substrate. Such a package is described and claimed in U.S. Pat. Nos. 4,245,273 and 4,302,625. U.S. Pat. Nos. 3,993,123 and 4,138,692 each disclose integrated circuit packaging structures ("Gas Encapsulated Cooling Modules") employing a multi-layer ceramic substrate with many semiconductor devices solder bonded thereto.
When the foregoing type of multiple semiconductor device module is used in mass production, especially for high performance computers, the need for replacing one or more devices may arise if the latter has been found defective. The probability of this need increases as the number of devices contained in the module increases. The need is for a method of removing the defective devices from a given site, preparing the site for a new device and subsequently joining the new device. Examples of the background technique related to the removal of the devices by thermal methods are given in IBM Technical Disclosure Bulletin in the articles "Use of a Heated Jet to Remove a Silicon Chip Soldered to a Substrate", by K. S. Sachar et al, Vol. 20, No. 9 Feb. 1978 P. 3725, and "Inverted Hot Gas Selected Chip Removal" by L. R. Cutting et al, Vol. 21, No. 9, Feb. 1979 P. 3592. However, the most difficult task is to re-condition the solder pads on the substrate after the device has been removed. This normally consists of eliminating the solder partially but not entirely at the pad site. It is desirable that such a method be rapid, simple, and of low cost. It must not affect the adjacent devices or damage the metallurgy network present on the substrate surface, or produce solder runs that might result in undesirable short circuits between the conductor stripes or pads.
The removal of solder bonded devices with known conventional device removal techniques leaves a great deal of solder on the pad of the substrate. The amount varies with the removal technique, but is usually in the range of 30% to 80% of the total amount of solder used in the solder bonds. This amount of solder is excessive and must be removed before a replacement device can be joined. Generally only 10-15% of the total solder should remain on the pads in preparation for a subsequent device joining operation. U.S. Pat. No. 4,444,559 is directed to a rework method for removing a solder bonded integrated circuit chip from a ceramic substrate leaving only a coating of solder on the pad site sufficient to solder bond another integrated circuit chip without the need for additional site preparation.
As briefly stated hereinabove a significant problem in the manufacture of integrated circuit modules is the removal and replacement of a single defective connector pin in an array of small closely spaced connector pins. This solution to the problem is to provide a method and apparatus for efficiently and economically accomplishing this task without adversely effecting the surrounding connector pins and the metal-ceramic interfaces of the surrounding pins and the pin under repair. Applicant's invention, as fully disclosed herein is directed to the solution of the above identified problem of connector pin removal and replacement. Applicants have carefully reviewed and experimented with a number of known prior art techniques of removing and replacing a single pin in a dense array and found them to be grossly unsatisfactory. The prior art techniques in the IBM Technical Disclosure Bulletin publications (fully identified hereinafter) by J. R. Lynch, J. J. Dankelman et al and J. Furrari, each directed to pinning or pin repair, have been reviewed.
As will be fully apparent from the detailed description hereinafter applicants' invention has particular utility and advantage when utilized to remove and replace a single connector pin an integrated circuit packaging structure having a sizeable array of closely spaced, small connector pins, such as employed in the commercial structure termed "Thermal Conduction Module" (TCM).
The high density packaging structure containing a plurality of interconnected semiconductor chips may be generally of the type disclosed in IBM NEWS SPECIAL EDITION November 1980, Copyright 1980 by International Business Machines. The high density packaging structure is termed a "Thermal Conduction Module".
The "Thermal Conduction Module" has a sizeable number of chip sites available, for example, 100 or 118. The chips are placed on--and are interconnected by--a large, multi-layer ceramic substrate whose power and input/output capability is provided through 1800 pins extending from the bottom of the substrate. The chip-populated substrate is placed in a cooling frame where spring loaded pistons that are part of the cooling "hat" subassembly come in contact with each chip. In addition to providing a housing for the pistons, the hat contains helium gas which also helps transmit heat from the chips. Subsequently, the hat is attached to a water (or liquid) cooled assembly.
The "Thermal Conduction Modules" multi-layer ceramic substrate is formed from sheets of unfired (green) ceramic, which are "personalized" according to the function each sheet is to perform. First, thousands of minute holes, or vias, are punched in each sheet. The wiring pattern which conducts the electrical signals, is formed by screening a metallic paste onto the sheet through a metal mask. The via holes are also filled with this paste to provide the electrical connections from one layer or sheet to another. The layers are stacked and laminate together under heat and pressure. The laminate is then sintered in a process which shrinks it. This results in a substrate of tile-like hardness with the desired electrical characteristics. Additional metals are plated on the substrate to provide reliable contact surfaces for subsequent chip placement and pin attachments as well as for adding wiring. A finished substrate may have dimensions in the order of 90 millimeters (3.5 inches) square and 5.5 millimeters (2/10 inch) thick.
In the "Thermal Conduction Module", for example, each pin of the dense array of closely spaced small connector pins is 0.090 inches (2.28 millimeters) in height 0.013 inches (0.33 millimeters) in diameter and uniformly space 0.100 inches (2.52 millimeters) from adjacent pins.
The technique of joining (connecting) the chips to the substrate may be generally in accordance with the method disclosed in U.S. Pat. No. 3,429,040 entitled "Method of Joining A Component To A Substrate" granted Feb. 25, 1969 to L. F. Miller.